
/*
**************************************************************************************************************
File:         top_ddr3.sv
Description:  Defines the testbench required for testing the DDR3 interface
Author     :  Rohit Kulkarni
              Aditya Joshi
**************************************************************************************************************
*/
`include "package.sv"

module top(input logic CK, OP, input logic [LOGICAL_ADDR_WIDTH-1:0] ADDR);
  
  DDR_bus bus(.*);                                        //instantiate a DDR3 bus
  
  controller  DDR_controller(.IF(bus.memory_controller), .*);    //will use the mem_cntrl modport view

endmodule